Stress engineering is an important technique for enhancing the performance of sub-100 nanometer (nm) metal-oxide semiconductor field-effect transistors (MOSFETs), and a variety of stress-inducing techniques have been developed. Earlier techniques have limitations; specifically, the magnitude of stress that a technique may deliver may not be sufficiently large. Also, for many previously developed techniques, the channel stress decreases as the device is scaled up. Therefore, there is continued interest in strain-inducing techniques that can provide large magnitudes of strain in the channel and whose effectiveness is not decreased with increased scaling.
A technique is provided for inducing strain in a MOSFET channel by using elastic relaxation of a thin, buried strained layer (e.g., a SiGe layer) to induce tensile strain in an overlying layer (e.g., a Si layer). Embodiments include relaxation via an creation of a free surface via an amorphization implant and anneal and/or removal of semiconductor material, creation of a free surface on top of a channel by amorphization and anneal of the gate and/or removal of a sidewall spacer, the use of an unusually large sidewall spacer to increase the strain for very short gate lengths, utilization of other strain-inducing techniques including stress memorization, and implementation of the technique on a strained semiconductor-on-insulator (SSOI) substrate or strained silicon on a SiGe graded buffer to reduce plastic relaxation of originally present strain.
The effectiveness of this technique is demonstrated through stress simulations of MOSFETs with a buried SiGe layer. The simulations were executed for different values of the key determinant of channel stress in a particular material system: a SiGe layer stress, a SiGe layer thickness, and an overlying silicon layer thickness. The design space is explored from Lg=25 nm to Lg=9 nm. More specifically, stress simulations were undertaken to examine the effectiveness of the technique in delivering stress to MOSFETs from the ITRS 65 nm node (Lg=32 nm) through the 22 nm node (Lg=13 nm). These simulations examined the preferred thicknesses of the two most important layers of the structure, the SiGe layer and the silicon layer disposed thereover, across technology generations. Large average stress levels [exceeding 1 gigapascal (GPa)] may be achieved using practically relevant thicknesses of silicon and SiGe. Significantly, the stress level appears to increase with decreasing gate length, so the technique is particularly relevant for future technology nodes.
In an aspect, the invention features a method for forming a structure. Embodiments of the method include forming a first crystalline strained semiconductor layer having a first lattice constant over a substrate. A second crystalline semiconductor layer having a second lattice constant different from the first lattice constant is formed on a top surface of the first crystalline semiconductor layer. A portion of the first crystalline semiconductor layer and a portion of the second crystalline semiconductor layer are amorphized and annealed to induce a change in the strain in the first crystalline semiconductor layer and in the second crystalline semiconductor layer.
One or more of the following features may be included. Amorphizing may include performing an amorphization implant, and/or annealing may include a rapid thermal anneal. The first crystalline semiconductor layer may include an alloy of silicon and germanium, or it may consist essentially of silicon.
Preferably, the substrate is, e.g., (100) silicon, a strained-silicon-on-insulator substrate or a strained-semiconductor-on-insulator substrate. A thickness of the first crystalline semiconductor layer may be greater than a critical thickness of the first crystalline semiconductor layer disposed over silicon.
In some embodiments, a thickness of the first semiconductor layer is greater than a critical thickness and annealing is performed at a temperature sufficiently low to prevent relaxation of the first semiconductor layer.
The structure may include an n-type field-effect transistor (N-FET). A strain-inducing overlayer may be disposed above the first crystalline semiconductor layer. The amorphized region may include a source or a drain of a field-effect transistor (FET).
In another aspect of the invention, a method for forming a structure is provided. In an embodiment, a first crystalline semiconductor layer is formed over a substrate, the first crystalline semiconductor layer being strained and having a first lattice constant. A second crystalline semiconductor layer is formed on a top surface of the first layer, the second crystalline semiconductor layer having a lattice constant different from the first lattice constant. A transistor is defined including a gate electrode, a source, a drain, and a channel region, the channel region including at least a portion of the second crystalline semiconductor layer. At least a portion of the gate electrode, source, and/or drain is amorphized to induce strain in the channel region.
Yet another aspect of the invention features a method for forming a structure. In an embodiment, a first crystalline semiconductor layer that is strained and has a first lattice constant is formed over a substrate. A second crystalline semiconductor layer having a lattice constant different from the first lattice constant is formed on a top surface of the first crystalline semiconductor layer. A transistor including a gate electrode disposed above the second crystalline semiconductor layer is formed, as well as a sidewall spacer adjacent the gate electrode, and a channel region disposed below the gate electrode and at least partially in the second crystalline semiconductor layer. A free surface is created above the channel region in the gate electrode and/or the sidewall spacer. The free surface induces strain in at least a portion of the channel region disposed in the second crystalline semiconductor layer.
Creating the free surface above the channel region may induce relaxation of strain in the first crystalline semiconductor layer disposed below the channel region. Creating the free surface may include removing the sidewall spacer and/or amorphizing and annealing at least a portion of the gate electrode. In some embodiments, the gate electrode may include an amorphous material. A strain-inducing overlayer may be formed above the first crystalline semiconductor layer.
In still another aspect, the invention involves a method for forming a structure. In an embodiment, a first crystalline tensilely strained semiconductor layer having a first lattice constant is formed over a substrate. A second crystalline semiconductor layer having a second lattice constant different from the first lattice constant is formed on a top surface of the first crystalline semiconductor layer. A transistor including a gate electrode, a source, a drain, and a channel region, is defined, with the channel region including at least a portion of the second crystalline semiconductor layer. A free surface is created in the gate electrode, source, and/or drain, with the free surface inducing compressive strain in the channel region.
The free surface may be created by amorphizing at least a portion of the gate electrode, source, and/or drain. In some embodiments, the free surface is created by removing at least a portion of the gate electrode, source, and/or drain.
Another aspect of the invention features a method for forming a structure. In various embodiments, first and second shallow trench isolation (STI) regions are formed in a substrate. A first strained crystalline semiconductor layer having a first lattice constant is formed over the substrate between the first and second STI regions. A second crystalline semiconductor layer having a second lattice constant different from the first lattice constant is formed on a top surface of the first crystalline semiconductor layer between the first and second STI regions. A first free surface is created in the first and second crystalline semiconductor layers, and a second free surface is created in the first and/or second STI regions. The first and second free surfaces induce a change in the strain in the first crystalline semiconductor layer and induce strain in the second crystalline semiconductor layer.
Creating the free surface in the first and second crystalline semiconductor layers may include amorphizing a portion of each of the first and second crystalline semiconductor layers or removing at least a portion of each of the first and second crystalline semiconductor layers. A FET having a channel region including at least a portion of the second crystalline semiconductor layer may be formed.
In still another aspect, the invention includes a method for forming a structure. In an embodiment, a first strained crystalline semiconductor layer having a first lattice constant is formed over a substrate. A second crystalline semiconductor layer having a second lattice constant different from the first lattice constant is formed on a top surface of the first layer. A transistor is formed, including (i) a gate electrode disposed above the second crystalline semiconductor layer, (ii) a sacrificial sidewall spacer adjacent the gate electrode, the sacrificial sidewall spacer having a first width, and (iii) a channel region disposed below the gate electrode, the channel region including at least a portion of the second crystalline semiconductor layer. At least a portion of the sacrificial sidewall spacer is removed to induce strain in the channel region disposed in the second crystalline semiconductor layer. A device sidewall spacer proximate the gate electrode is defined, the device sidewall spacer having a second width smaller than the first width.
In another aspect, the invention features a method for forming a structure. Embodiments include forming a first strained semiconductor layer including a first semiconductor material over a substrate comprising a crystalline material. A second relaxed semiconductor layer, including a second semiconductor material, is formed over the first semiconductor layer. A metal gate electrode is formed over the second semiconductor layer. The metal gate electrode is annealed to a temperature sufficient to allow stress relaxation in the metal gate electrode Annealing the metal gate electrode relaxes at least a portion of the first semiconductor layer, and relaxation of the first semiconductor layer portion induces strain in at least a portion of the second semiconductor layer.
In yet another aspect, the invention features a structure. In an embodiment, the structure includes a first layer includes a first strained semiconductor material disposed above a substrate. A second layer, including a second semiconductor material different from the first semiconductor material, is disposed on the first layer. A transistor gate electrode and a sidewall spacer are disposed above the second layer, the gate electrode and sidewall spacer defining a first region disposed thereunder and including a first portion of each of the first and second layers. A second region is disposed laterally and spaced apart from the first region, extends into the first and second layers, and comprising a third material. The composition and/or defect density of the second region is different from a composition and/or defect density of the first region.
One or more of the following features may be included. The third material may be the same as the first semiconductor material or the second semiconductor material. The third material may be different from the first and second semiconductor materials. The third material may include a second portion of each of the first and second layers, the second portions having substantially higher crystalline defect densities than the first portions. A strain-inducing overlayer may be disposed above the first layer, the gate electrode, and sidewall spacer.